阿里云 外貿(mào)網(wǎng)站,泰安百度貼吧,網(wǎng)站信息架構(gòu)圖怎么做,企業(yè)網(wǎng)站管理系統(tǒng)有哪些今天我們先嘗試一下debug這是代碼塊示意圖這是原代碼always (*) beginif (cpu_overheated)shut_off_computer 1; end always (*) beginif (~arrived)keep_driving ~gas_tank_empty; end可以發(fā)現(xiàn)這個(gè)代碼無(wú)法實(shí)現(xiàn)圖片功能#xff0c;因此我們需要進(jìn)行修改#xff0c;有兩個(gè)l…今天我們先嘗試一下debug這是代碼塊示意圖這是原代碼always (*) begin if (cpu_overheated) shut_off_computer 1; end always (*) begin if (~arrived) keep_driving ~gas_tank_empty; end可以發(fā)現(xiàn)這個(gè)代碼無(wú)法實(shí)現(xiàn)圖片功能因此我們需要進(jìn)行修改有兩個(gè)latch鎖存器組合邏輯在任何情況下所有輸出都必須被賦值。這通常意味著必須寫(xiě)else或者在always一開(kāi)始給一個(gè)default 值eg1always (*) begin shut_off_computer 1b0; // 默認(rèn)值 if (cpu_overheated) shut_off_computer 1b1; endcase1 case語(yǔ)句Verilog 中的case 語(yǔ)句在功能上幾乎等價(jià)于一串if – else if – else用于將一個(gè)表達(dá)式與多個(gè)候選值進(jìn)行比較。eg2module top_module ( input [2:0] sel, input [3:0] data0, input [3:0] data1, input [3:0] data2, input [3:0] data3, input [3:0] data4, input [3:0] data5, output reg [3:0] out );// always(*) begin // This is a combinational circuit out4b0; case(sel) 3b000:begin out data0; end 3b001:begin out data1; end 3b010:begin out data2; end 3b011:begin out data3; end 3b100:begin out data4; end 3b101:begin out data5; end endcase end endmodulecase2實(shí)現(xiàn)一個(gè)優(yōu)先編碼器優(yōu)先編碼器priority encoder是一種組合邏輯電路當(dāng)輸入一個(gè)比特向量bit vector時(shí)它會(huì)輸出第一個(gè)為 1 的比特所在的位置module top_module ( input [3:0] in, output reg [1:0] pos ); always (*)begin pos2b0; case(in) 4b0000:begin pos 2d0; end 4b0001:begin pos 2d0; end 4b0011:begin pos 2d0; end 4b1001:begin pos 2d0; end 4b0101:begin pos 2d0; end 4b1101:begin pos 2d0; end 4b1011:begin pos 2d0; end 4b0111:begin pos 2d0; end 4b1111:begin pos 2d0; end 4b0010:begin pos 2d1; end 4b1010:begin pos 2d1; end 4b0110:begin pos 2d1; end 4b1110:begin pos 2d1; end 4b0100:begin pos 2d2; end 4b1100:begin pos 2d2; end 4b1000:begin pos 2d3; end endcase end endmodule用if語(yǔ)句更簡(jiǎn)單module top_module ( input [3:0] in, output reg [1:0] pos ); always (*) begin if (in[0]) pos 2d0; else if (in[1]) pos 2d1; else if (in[2]) pos 2d2; else if (in[3]) pos 2d3; else pos 2d0; // in 全 0 的情況必須有 end endmodulecasez支持高阻輸入當(dāng)成來(lái)處理module top_module ( input [7:0] in, output reg [2:0] pos ); always(*)begin pos 3b0; casez(in) 8b00000000:pos 3d0; 8bzzzzzz10:pos 3d1; 8bzzzzz100:pos 3d2; 8bzzzz1000:pos 3d3; 8bzzz10000:pos 3d4; 8bzz100000:pos 3d5; 8bz1000000:pos 3d6; 8b10000000:pos 3d7; endcase end endmodulecase3 游戲編輯器假設(shè)你正在為一個(gè)游戲設(shè)計(jì)電路用來(lái)處理PS/2 鍵盤(pán)傳來(lái)的掃描碼scancode,給定最近接收到的兩個(gè)字節(jié)16 位的掃描碼你需要判斷是否有某個(gè)方向鍵被按下。掃描碼與方向鍵的對(duì)應(yīng)關(guān)系Scancode (16-bit)方向鍵16he06b左16he072下16he074右16he075上其他無(wú)module top_module ( input [15:0] scancode, output reg left, output reg down, output reg right, output reg up ); always(*)begin left 0; down 0; right 0; up 0; case(scancode) 16he06b:left 1b1; 16he072:down 1b1; 16he074:right 1b1; 16he075:up 1b1; endcase end endmodule